1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a dynamic random access memory capable of performing refresh operation independently of input signals externally supplied (which will hereinbelow be referred to as a xe2x80x9ccomplete-hidden-refresh-function-included DRAMxe2x80x9d).
2. Description of the Background Art
In a field of portable terminals such as portable telephones, there is widely used an asynchronous general-purpose static ramdom access memory (which will hereinbelow referred to as xe2x80x9cSRAMxe2x80x9d) for which external clocks need not be supplied. In the SRAM, since refresh operation need not be performed, complex control need not be performed. For example, the SRAM need not perform control access that is made to the memory in refresh operation by awaiting completion of a refresh cycle. For this reason, with the SRAM being used, since the system configuration can be simplified, the SRAM is therefore suitable for use with the portable terminal.
Recently, the function of portable terminal has been significantly improved, and the terminal requires large scale memory functions. However, the SRAM has memory which is about 10 times that of a dynamic ramdom access memory (which hereinbelow will be referred to as a xe2x80x9cDRAMxe2x80x9d). For a large-scale SRAM, the cost for the memory chip is significantly increased, and consequently, the price of the portable terminal is increased. To overcome the problem, a new technical scheme was conceived in which, instead of the SRAM, a DRAM of which memory cost per unit bit is relatively lower is used with the portable terminal.
However, the DRAM requires complex memory control relative to refresh operation. For portable-terminal manufacturers that hitherto have been engaged in design of systems using SRAMs as memories, it is not easy to use DRAMs as substitutive memories of SRAMs.
Under these circumstances, many semiconductor manufacturers have begun the development of a new semiconductor memory device. The new memory device is formed of a DRAM, but it operates as a SRAM in terms of external functions. A semiconductor memory device of the new type is reported in the publication xe2x80x9cKazuhiro Sawada, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 1, February 1998, (pp.12-19)xe2x80x9d.
In the new semiconductor memory device, the same memory cells as those used in the DRAM are used. On the other hand, external interfaces, such as control signals and address signals to be input to the semiconductor memory device, are the same as those to be input to the SRAM. However, different from refresh operation or self-refresh operation of the conventional DRAM, refresh operation of the new semiconductor memory device is not controlled by signals received from an external source. In specific, the refresh operation is controlled by a refresh command signal /REFE that is cyclically output from a refresh circuit provided in the complete-hidden-refresh-function-included DRAM. The refresh circuit includes a ring oscillator as a timer circuit, and outputs refresh command signal /REFE in response to a cycle signal /Refcyc that is cyclically output from the timer circuit. Since the timer circuit thus outputs cycle signal /Refcyc all the time, the semiconductor memory device of the new type cyclically executes refresh operation either in an operation state where read operation or write operation is executable or in a standby state.
Based on the function, the new semiconductor memory device hereinbelow will be referred to as a xe2x80x9ccomplete-hidden-refresh-function-included DRAMxe2x80x9d. The development of the complete-hidden-refresh-function-included DRAM satisfies requirements for improvement in the function of portable terminals.
As described above, however, in the complete-hidden-refresh-function-included DRAM, the refresh operation is executed either in the operation state or in the standby state. In this case, a malfunction can occur when refresh command signal /REFE and a write-or-read operation request signal are activated with the same timing.
FIG. 8 is a timing chart representing a case where a malfunction occurs in a conventional complete-hidden-refresh-function-included DRAM.
Referring to FIG. 8, a chip enable signal /CE is a control signal externally input. When chip enable signal /CE is active, the complete-hidden-refresh-function-included DRAM is in an operation state. When chip enable signal /CE is inactive, the complete-hidden-refresh-function-included DRAM is in a standby state.
In the timing chart shown in FIG. 8, since chip enable signal /CE is inactive (H level) before a time t4, the complete-hidden-refresh-function-included DRAM enters the standby state. In the standby state, at a time t1 and a time t3, refresh command signal /REFE is activated in response to cycle signal /Refcyc, and refresh operation is executed. On the other hand, at a time t2 whereat cycle signal /Refcyc is inactive, since refresh command signal /REFE is inactive, the complete-hidden-refresh-function-included DRAM does not perform refresh operation.
Subsequently, when chip enable signal /CE becomes active (L level) at time t4, the complete-hidden-refresh-function-included DRAM enters the operation state.
In the above, similarly to the case of a time t5, in the activation of refresh command signal /REFE, a case can occur in which a write-or-read operation request signal is externally input. In this case, the complete-hidden-refresh-function-included DRAM causes a malfunction.
To prevent such a malfunction, a conventional complete-hidden-refresh-function-included DRAM has an arbitration circuit.
The arbitration circuit compares the synchronous signals, namely, refresh command signal /REFE and the externally input write-or-read operation request signal, and arbitrates the operational priority thereof. In practice, when refresh command signal /REFE and the write-or-read operation request signal have been activated with the same timing, the arbitration circuit carries out arbitration in such a manner that operation of one of the signals which is activated earlier is executed earlier, and operation of the other one of the signals is then executed.
Because of the above configuration, even when refresh command signal /REFE and the write-or-read operation request signal are activated with the same timing, malfunction of the complete-hidden-refresh-function-included DRAM can be prevented to a certain extent.
However, in the case where the arbitration circuit performs arbitration such that the write-or-read operation is executed after the refresh operation, the probability of delay in access speed is thereby increased. In addition, when refresh command signal /REFE and the write-or-read operation request signal are activated with exactly the same timing, arbitration therefor cannot be achieved by the arbitration circuit.
Because of the above-described problems, the conventional complete-hidden-refresh-function-included DRAM encounters difficulties in ensuring the stability in the refresh operation.
An object of the present invention is to provide a semiconductor memory device that can be set to an operation state in which read/write operation for data is executable and a standby state in which the data is retained and that enables the stability of refresh operation to be ensured.
A semiconductor memory device of the present invention can be set either to an operation state where a read operation or a write operation for data is executable or to a standby state where the data is retained. The semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in a matrix, and a complete hidden refresh circuit for performing refreshing operation without being externally commanded for the data stored in the plurality of memory cells. The complete hidden refresh circuit executes the refresh operation according to the condition of the semiconductor memory device.
The complete hidden refresh circuit preferably executes the refresh operation when the semiconductor memory device is in the standby state.
In the semiconductor memory device arranged as above, the refresh operation and a write-or-read operation are not executed with the same timing.
In addition, the complete hidden refresh circuit preferably executes the refresh operation after completion of the read operation of the semiconductor memory device.
Furthermore, the complete hidden refresh circuit preferably executes the refresh operation after completion of the write operation of the semiconductor memory device.
In the semiconductor memory device arranged as above, the refresh operation is not executed during one of the read operation and write operation.
Still furthermore, the complete hidden refresh circuit preferably includes a refresh circuit for outputting a refresh command signal for execution of the refresh operation, and a control circuit for executing the refresh operation in response to the refresh command signal. The refresh circuit preferably includes a timer circuit for outputting a cycle signal at a time interval necessary for refreshing data stored in the plurality of memory cells, a command-signal activating circuit for activating the refresh command signal in response to the cycle signal, and a determination circuit for determining as to whether or not the refresh command signal activated is to be output.
Still furthermore, the determination circuit preferably determines that the refresh command signal activated is to be output when the semiconductor memory device is in the standby state.
In the semiconductor memory device arranged as above, the refresh operation and a write-or-read operation are not executed with the same timing.
Still furthermore, the determination circuit preferably determines that the refresh command signal activated is to be output after the semiconductor memory device has completed the read operation.
Still furthermore, the determination circuit preferably determines that the refresh command signal activated is to be output after the semiconductor memory device has completed the write operation.
In the above-described semiconductor memory device, the refresh operation is performed after completion of the write-or-read operation. Consequently, the write-or-read operation and the refresh operation are not executed with the same timing, thereby enabling stabilized refresh operation to be executed.
According to the present invention described above, the semiconductor memory device including the complete hidden refresh function is capable of preventing refresh operation and read-or-write operation from being executed with the same timing. Furthermore, this reduces the probability at which access is delayed in read-or-write operation. Still furthermore, the stability in refresh operation can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.